VLSI Design Premium Lecture Notes, Prepared by Thenmozhi. Specially for Electronics and Communication Engineering. Syllabus Covered based on Anna University B.E Electronics and Communication Engineering
CONTENT:
VLSI DESIGN
UNIT-III (Pages: 58)
SEQUENTIAL LOGIC CIRCUITS
UNIT- IV (Pages: 46)
DESIGNING ARITHMETIC BUILDING BLOCKS
UNIT-V ( Pages: 24)
IMPLEMENTATION STRATEGIES
Attachment: click here
UNIT-III
SEQUENTIAL LOGIC CIRCUITS
Static latches
Static register
Metal stability
Dynamic latches and register
Dynamic latches
Dynamic transmission
Disadvantages of dynamic register
Positive edge trigger register
CMOS clocked register
Advantages
Timing issues
1. Timing parameters for combinational circuits
2. Propagation delay
3. Contamination delay
Timing parameters for sequential logic
Pipe lining
Clocking strategies
Global clock generation
Global clock distribution
H – Trees
Local clock gaters
Memories
Introduction
Memory array architecture
Static RAM
SRAM basics
CMOS SRAM cell
READ operation
WRITE operation
SRAM write circuitry
Dual port SRAM
Dynamic read-write memory
Read only memory
ROM cell NAND based ROM
Memory peripheral circuitry
UNIT- IV
DESIGNING ARITHMETIC BUILDING BLOCKS
Introduction of adder
Classification of adder
Basic adder
1. Half adder
2. Full adder
Parallel adder
Ripple carry adder
Carry look ahead adder
Carry speed adder
Carry select adder
Manchester adder
Manchester dynamic carry propagation circuit
Multipliers
Array multipliers
Baugh – wooley multipliers
Barrel shifter
Booth’s multipliers
Shifter
Array shifter
Short circuit power dissipation
Gate induced drain leakage
Gate oxide tunneling
Sub threshold leakage current
Leakage power dissipation
Static power dissipation
UNIT-V
IMPLEMENTATION STRATEGIES
VLSI design styles
Full custom design
Advantages
Disadvantages
Semi custom design
Standard cell based design
Advantages
Disadvantages
Features
Standard cell library
Gate array based ASIC’S
Types of masked gate array
Channeled gate array
Channel less gate array
Structural gate array
Advantages
Disadvantages
Features
Programmable logic device PLD
Programmable array logic
Characteristics of FPGA
Complex programmable logic devices
Programmable logic array
Field programmable gate array
FPGA building block architecture
Configurable logic block
Xilinx logic block
Actel logic block
Alterate logic block
Programmable interconnect
Attachment: click here
