AU R2004 EC1312 Digital Logic Circuits May June 2014 Question Paper

[aaru]

   

Question Paper Code : 53386 

B.E./B:Tech. DEGREE EXAMINATION, MAY/JUNE: 2014. 

Fifth Semester 

Electrical and Electronics Engineering 

EC 1312— DIGITAL LOGIC CIRCUITS 

(Common to Fourth Semester — Instrumentation and Control Engineering and Electronics and Instrumentation Engineering) 

(Regulation 2004) 

(Common to B.E. (Part — Time) Fourth Semester — Electrical and Electronics Engineering — Regulation 2005)

Time : Three hours 
Maximum : 100 marks

Answer ALL questions. 
PART A  (10 x 2 20 marks) 
1.Convert the hexadecimal number - A2BEF to binary. 
2.Realise AND gate using only NAND gates. 
3.Draw the logic diagram for half adder. 
4.Define multiplexer. 
5.How many flip flops are required to design mod 30 binary counter? 
6.Draw the logic diagram for JK flip flop. 
7.Define race conditions in Asynchronous sequential circuit. 
8.What is the basic difference between synchronous sequential circuit and asynchronous sequential circuit? 
9.Write the two primary differences between WINL and CMOS. 
10.What are the advantages of PIA? 

Full Name :Arumugam.P
College Name :SNS College Of Technology
Department :EEE
Semester :05
Subject Code :EC1312
Subject Name : Digital Logic Circuits
Study Material Description :QP

Attachment :

  DLC MJ2014 QP.pdf (Size: 1.19 MB / Downloads: 158)

[Srini]

+1