Training Programme on
FPGA IMPLEMENTATION OF DIGITAL SYSTEMS USING ALTERA QUARTUS II
27th& 28th FEB 2014
ORGANISED BY
IEEE STUDENT BRANCH
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
ANNA UNIVERSITY
REGIONAL CENTRE, COIMBATORE
Mettupalayam Road, Jothipuram
Coimbatore – 641 047
FPGA IMPLEMENTATION OF DIGITAL SYSTEMS USING ALTERA QUARTUS II
27th& 28th FEB 2014
ORGANISED BY
IEEE STUDENT BRANCH
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
ANNA UNIVERSITY
REGIONAL CENTRE, COIMBATORE
Mettupalayam Road, Jothipuram
Coimbatore – 641 047
ABOUT ALTERA QUARTUS
Altera Quartus is programmable logic device design software from Altera Inc. The basic feature includes, implementation of VHDL and Verilog for hardware description, visual edition of logic circuits and vector waveform simulation in a single package. It is a software tool produced by Altera for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target FPGA device with the programmer. It helps engineers in overcoming the design challenges in the increasingly complex worlds of logical synthesis and FPGA implementation.
Altera Quartus is programmable logic device design software from Altera Inc. The basic feature includes, implementation of VHDL and Verilog for hardware description, visual edition of logic circuits and vector waveform simulation in a single package. It is a software tool produced by Altera for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target FPGA device with the programmer. It helps engineers in overcoming the design challenges in the increasingly complex worlds of logical synthesis and FPGA implementation.
WHO SHOULD ATTEND?
The faculties, final year UG and PG students from Engineering Colleges who have interest in VLSI layout design and doing research in the area of VLSI Design using Front End tools.
TOPICS TO BE COVERED
• Quartus II Software overview with basic FPGA design.
• Various Analysis available in Quartus.
• Design and implementation for combinational circuits and sequential circuits.
• Functional Verification and implementation on FPGA Kits.
• FPGA Implementation of Real Time Clock in seven segment display.
REGISTRATION
Registration for the training program can be done using the attached form or photo copy of the form. The completed form could be sent by post to the Coordinator. The Registration is restricted to first 40 participants only. For spot registration contact the coordinator.
IMPORTANT DATE
Last Date of Registration: 25th Feb 2014
FEE DETAILS
IEEE Non-IEEE
Students / Faculty : ₹ 900/- ₹ 1,000/-
Industry delegates : ₹1,350/- ₹ 1,500/-
DD should be drawn in favour of “IEEE Student Branch – AUCBE” Payable at Coimbatore, Tamil Nadu, India
Registration form and Brochure :
Altera Workshop 27 and 28 Feb 2014.pdf (Size: 92.61 KB / Downloads: 164)
TOPICS TO BE COVERED
• Quartus II Software overview with basic FPGA design.
• Various Analysis available in Quartus.
• Design and implementation for combinational circuits and sequential circuits.
• Functional Verification and implementation on FPGA Kits.
• FPGA Implementation of Real Time Clock in seven segment display.
REGISTRATION
Registration for the training program can be done using the attached form or photo copy of the form. The completed form could be sent by post to the Coordinator. The Registration is restricted to first 40 participants only. For spot registration contact the coordinator.
IMPORTANT DATE
Last Date of Registration: 25th Feb 2014
FEE DETAILS
IEEE Non-IEEE
Students / Faculty : ₹ 900/- ₹ 1,000/-
Industry delegates : ₹1,350/- ₹ 1,500/-
DD should be drawn in favour of “IEEE Student Branch – AUCBE” Payable at Coimbatore, Tamil Nadu, India
Registration form and Brochure :
Altera Workshop 27 and 28 Feb 2014.pdf (Size: 92.61 KB / Downloads: 164)
