Anna University , Chennai
Department of Electronics and Communication Engineering
Sixth Semester
EC2354 VLSI Design
May June 2014 Important Questions
(Regulation 2008)
Attachment :
VLSI IMP 2014.pdf (Size: 212.87 KB / Downloads: 2,766)
UNIT 1
1. Derive the CMOS inverter DC characteristics and obtain the relationship for output voltage at different region in the transfer characteristics.
2. Explain with neat diagrams the various CMOS fabrication technology
3. Explain the latch up prevention techniques.
4. Explain the silicon semiconductor fabrication process.
5. Explain various CAD tool sets
UNIT 2
1. Explain the operation of PMOS Enhancement transistor
2. Explain the threshold voltage equation
3. Explain the operation of NMOS Enhancement transistor.
4. Explain the Transmission gate and the tristate inverter briefly.
5. Explain about the various non ideal conditions in MOS device model.
UNIT 3
1. Explain the concept of MOSFET as switches
2. Explain the ASIC design flow with a neat diagram
3. Explain the concept of Delay estimation, logical effort and sizing of MOSFET
UNIT 4
1. Explain fault models.
A) Stuck-At Faults
B) Explain ATPG.
2. Briefly explain
a) Fault grading & fault simulation
b) Delay fault testing
c) Statistical fault analysis
3. Explain scan-based test techniques.
4. Explain self-test techniques and IDDQ testing.
5. Explain system-level test techniques
UNIT 5
1. Explain with neat diagrams the Multiplexer and latches using transmission Gate.
2. Explain the concept of gate delay in VERILOG with example
3. Explain the concept of MOSFET as switches and also bring the various logic gates using the switching concept.
4. Explain the concept involved in structural gate level modeling and also give the description for half adder and Full adder.
5. Explain the VLSI design flow with a neat diagram.
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