Anna University
Department of Electronics and Communication Engineering
Third Semester
EC2203 Digital Electronics
(Regulation 2008)
Unit 1
1. Find the minimum sum of products expression using K-map for the function F=∑m(7,9,10,11,12,13,14,15) and realize the minimized function using only NAND gates.
2. Obtain simplified POS using k-map for
F (a, b, c, d) = ∑ (0, 2, 3, 4, 8, 10, 12, 13, 14)
3. Find the reduced SOP form of the following function: f(A, B, C, D) = ∑m(1, 3, 7, 11, 15) + ∑d(0, 2, 4).
4. Simplify using Quine-McClusky method F = ∑m(0, 1, 2,3,10, 11,12,13,14,15) (16)
5. Simplify using tabulation method. F (V, W, X, Y, Z) = ∑(4, 5, 6, 7, 9, 10, 14, 19, 26, 30, 31) Note: Quine-McClusky method is also called tabulation method (16)
6. Simplify the following functions and draw the logic diagram for the same. (6)
F1 = f(A, B, C) = ∑ (1, 2, 3, 5)
F2 = f(A, B, C) = ∑ (1, 3, 5, 7)
F3 = f(A, B, C) = ∑ (2, 3, 4, 5)
Unit 2
1. Design a multiplier circuit to multiply the following binary number
A = A0A1A2 and B = B0B1B2B3 using required number of binary parallel adders.
2. Design a binary to BCD converter
3. Design a logic circuit to convert the 8421 BCD to excess-3 code.
4. Design and implement a 8421 to Gray code converter. Realize the converter using only NAND gates.
5. Design a logic circuit to convert BCD to Gray code
Unit 3
1. Explain in detail the operation of a 4-bit binary ripple counter.
2. Explain in detail the operation of a 3-bit binary synchronous counter.
3. Design a BCD up/down counter using SR flip-flops.
4. Design BCD ripple counter using JK flip-flop.
5. Design a mod – 10 synchronous counter and draw the timing diagram of it.
Unit 4
1. Explain the basic structure of 256 x 4 static RAM with neat sketch.
2. Briefly explain about FPGA with a neat block diagram
3. Design a combinational circuit using a ROM. The circuit accepts a three bit number and outputs a binary number equal to the square of the input number.
4. Design a full adder using a suitable PROM.
5. Implement the given functions using PROM
F1 = ∑ (0, 1, 3, 4, 6, 7)
F2 = ∑ (1, 2, 3, 5)
6. Implement the following Boolean functions with a PLA.
F1 (A, B, C) = ∑ (0, 1, 2, 4)
F2 (A, B, C) = ∑ (0, 5, 6, 7)
F3 (A, B, C) = ∑ (0, 3, 5, 7)
Unit 5
1. For the circuit shown in figure, write down the state table and draw the state diagram and analyze the operation.
2. Design a T-FF giving the flow table, state table, state assignment, excitation table and excitation map.
3. Design an asynchronous sequential circuit that has 2 inputs X2 and X1 and one output z. When X1=0 ,the output z is O. The first change X2 that occurs while X1 is 1will cause output Z to be 1. The output Z will remain 1 until X1 returns to 0
4. What is a hazard? Explain the different types of hazards. What is an essential hazard? Discuss in detail how hazards can be eliminated.
5. Reduce the state table using implication chart method
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