Computer Architecture And Organization (CAO) Scanned Lecture Notes (Units 1, 2 and 4)

  • 10Jan
  • 2015
  • 0
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    Anna University , Chennai
    Department of B.E-Electronics and Communication Engg
    Fifth Semester
    EC2303 Computer Architecture And Organization
    (Regulation 2008)


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    Content : 
    COMPUTER ARCHITECTURE AND ORGANIZATION

    Computer architecture
    Computer organization
    Computing
    Application
    Evolution of computer
    Automated computing device
    Computer generation
    First generation
    Second generation 
    Third generation
    Basic functional units of a computer
    VLSI ERA
    IC
    IC density
    IC families
    Processor architecture
    Main frame
    Mini computer 
    Micro computer
    Performance considerations
    Performance measure
    Speedup technique
    Pipelined processing
    System architecture
    ARPANET
    Pocket switching
    Basic operational concepts
    Program counter
    CPU organization
    Accumulator based CPU
    CPU operation
    DATA REPRESENTATION
    Information
    Word length
    Fixed point number
    Decimal number
    BCA
    Floating point number

    UNIT-1
    Instruction and instruction sequencing
    Four types computer performance
    1. Data transfer between memory and processor register
    2. Arithmetic and logic operation on data
    3. Program sequencing and control
    4. Input and output transfer
    Register transfer notation
    Assembly language notation
    Basic instruction type
    Addressing modes
    1. Register mode
    2. Absolute mode
    3. Immediate mode
    4. Indirect mode
    5. Index addressing mode
    6. Relative addressing mode
    7. Auto increment mode
    System design
    System representation
    Computer aided design
    Register level components
    Register level design
    Processor level components
    Instruction format

    UNIT-2
    Addition and subtraction of signed number
    BINARY ARITHENATIC
    Block diagram
    Signed operand multiplication
    Fast multiplication
    Bit pair recoding of multiplier
    Adders
    Subtracter
    Division
    Implementing floating point operation
    Co-processors
    Pipe line processing
    Hard wired control
    1. Hard wired control
    Pipe line structure
    Microprogrammed control
    Micro instruction

    UNIT-4

    MEMORY DEVICES
    Classification of memories
    RAM
    1. SRAM
    2. DRAM
    ROM
    1. PROM
    2. EPROM
    3. EEPROM
    RAM organization
    Static organization
    Read operation
    Write operation
    Bipolar RAM
    Dynamic RAM cell
    Advantages
    Disadvantages
    ROM organization
    ROM cell
    Bipolar ROM
    Memory decoding
    1. Absolute decoding
    2. Linear decoding
    Interrupt
    Interrupt generation
    Handling interrupt
    Interrupt selection
    Vectored interrupt
    Memory mapped input
    Operating system
    Virtual memory
    Address translation
    Translation lookaride buffer

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