Anna University
CS2202 / 141302 Digital Principles and Systems Design IMPORTANT 16marks
(DPSD)
Subject Code : CS2202
Subject Name :Digital Principles and Systems Design
Department :CSE and IT
Semester :3
16 Marks
UNIT I
1 (i). Express the Boolean function F =A+B’C in sum of minterms
(ii) Express the Boolean function F=xy+x’z in production of maxterms.
Solution:
F = A+B’C
= A’B’C’+AB’C+AB’C+ABC’+ABC
= m1 + m4 + m5 + m6 + m 7
=_m (1,4,5,6,7)
F = XY+X’Z
= (X+Y+Z)(X+Y’+Z)(X’+Y+Z)(X’+Y+Z’)
= M 0 M 2 M 4 M 5
= P (0,2,4,5)
2.Simplify the Boolean function F(A,B,C,D)= _(0,6,8,13,14) Together with the don’t
care condition d=_(2,4,10)and then express the simplified function in sum of
minterms.
¨ Using 4-variable map simplify the function as
F=B’D’+CD’+ABC’D
¨Represent the simplified function in SOP from as
F=_(0,2,6,8,10,13,14)
3.Implement the Boolean function F(X,Y,Z)=(1,2,3,4,5,7)with NAND gates
¨Simplify the function using 3-varabile map and express it SOP from as
F=XY’+X’Y+Z
¨Draw a NAND gate for each product term of the expression. This gives a
group of first level gates.
¨Draw a single gate using the AND –invert or the invert -OR graphic simple
in the second level, with inputs coming from outputs of first level gates.
4. Simplify the Boolean function F(A,B,C,D) =_(0,2,3,5,7,8,9,10,11,13,15)and find the
prime implicants and essential prime implicants
¨ Simplify the expression using 4-varible map,
¨ Prime implicants are :CD,B’C,AD AND AB’
¨ Essential prime implicants are :CD,B’C,AD AND AB’
¨ Different simplified versions are :BD and B’D’
F=BD+B’D+CD+AD
F=BD+B’D+CD+AB’
F=BD+B’D+B;C+AD
F=BD+B’D’+B;C+AB’
5.Minimize the following function sing Quine Mc Cluskey Method
• List all minterms in the binary form
• Arrange minterms according to categories of 1 in a table
• Compare each binary number with every term in the next higher category and if
they differ only one position put a check mark and copy the term in the next
column with a – in the position that they differed.
• Continue the process until no further elimination of literals
• List the prime implicants
• Select the minimum number of prime implicants
UNIT II
1.Design a full adder with inputs x,y,z and two outputs S and C . The circuit performs
x+y+z, z is the input carry, C is the output carry and S is the Sum.
• Truth table for full adder
• Simplify using K map
• Draw the logic diagram using AND and XOR gate
• Draw the logic diagram using 2 half adders
2. Design a BCD adder.
• Explanation on BCD addition
o Add 2 BCD numbers using ordinary binary addition
o If sum >=9 no correction is needed
o If sum >=9 or if a carry is generated the sum is invalid
o To correct the invalid sum add 0110 to the sum. If a carry results from this
addition add it to the next higher order BCD digits.
• Draw the truth table with 4 inputs
• Simplify output using 4 variable map
• Draw the logic diagram
3. Design a logic circuit that accepts a 4-bit Grey code and converts it into 4-bit
binary code
• Draw the truth table with 4 inputs G3,G2,G1andG0 and 4 0utputs D,C,B and
A.
• Simplify the columns A,B,C and D using 4-variables map
A=(G3 XOR G2)XOR(G1 XOR G0)
B=G3 XOR G2 XOR G1
C=G3 XOR G2
D=G3
• Draw the logic diagram using xor gates with G3,G2,G1 and G0 as Input and
A,B,C and D as output
4.Write short notes on: BCD adder, Binary multiplier and Magnitude Comparator
o BCD adder truth table
o Block diagram of BCD adder
o Logic diagram for 2-bit by 2-bit binary multiplier
o 4-bit magnitude comparator
5.Explain in detail the Hardware Description Languages
• Module representation
• Gate delays
• Boolean expressions
• User -defined primitives
• Explanation of the above with suitable examples
UNIT-III
1.Draw the circuit for 3-to-8-decoder and implement the functions
F1(A,B,C)=II(0,1,3,7)
F2(A,B,C)=II(2,3,7) using 3-to-8-decoder
• Truth table for a 3-to-8-decoder(i/p: E,A,B,C and o/p:Y7-Y0)
• Logic diagram
• Block diagram of 3:8 decoder using IC74LS183 WITH A,B,C as input and
F1,F2 as output
2.Draw the circuits for Decimal to BCD encoder, Octal-to-Binary encoder & Priority
encoder
• Decimal to BCD encoder-logic symbol(74LS147,truth table)
• Octal to binary encoder truth table with inputs D0 - D7 and outputs A , B
and C
• Logic diagram of Octal to binary encoder: A=D4+D5+D6+D7;
B=D2+D3+D6+D7; C=D1+D3+D5+D7
• Priority encoder - truth table with i/ps : D0,D1,D2,D3 and o/ps: Y1,Y0,V
• Logic diagram of Priority encoder where Y1=D2+D3,Y0=D3+D1D2',
V=D1+D2+D3
3.Implement the following boolean function using 8:1 multiplier
• F(A,B,C,D)=A'BD'+ACD+B'CD+A'B'CD+A'BC'D+A'B'C'D
• Draw the Truth table for the above SOP(I/P's:A,B,C,D, o/p: Y)
• Draw the implementation table 8:1 multiplexer, where
D0=0,D2=0,D1=D3=1,D4=D5=D6=A',D7=A
4.Implement full subtractor using demultiplexer
• Truth table of full subtractor(i/p:A,B,Bin,o/pL
,Bout)
• D=F(A,B,C)= m(1,2,4,7)
• Bout=F(A,B,C)= m(1,2,3,7)
• Draw 1:8 demultiplexer with the input Din=1 and output D and Bout.
5.Implement the following Boolean function with a PLA
F1(A,B,C)= m(0,1,2,4)
F2(A,B,C)= m(0,5,6,7)
• Simplify F1 and F2 using k-map
F1(A,B,C)=(AB+AC+BC)'
F2(A,B,C)=AB+AC+A'B'C'
• Draw the PLA programming table with minterms
AB,AC,BC&A'B'C'
UNIT IV
1. Draw the state diagram and characteristic equations of T,D and JK flip flop
• Characteristic equation of T flip flop: Q(t+1)=TQ'+T'Q
• Characteristic equation of D flip flop: Q(t+1)=D
• Characteristic equation of JK flip flop: Q(t+1)=JQ'+K'Q
• state diagrams of T,D and JK flip flops
2. Write short notes on state reduction and state assignment in Sequential circuit
design
State reduction
• Given a state diagram of a sequential circuit. Establish the
corresponding state table
• Find the equivalent states that produce the same output for every
input and the same next state
• Draw the reduced state table by removing one of the equivalent
state
• Draw the corresponding reduced state diagram
State assignment
• Binary assignment
• Gray code assignment
• One-hot assignment
3. Discuss in detail shift registers
• Block diagram of 4-bit shift register
• Serial transfer of information
• serial addition using shift register
• Universal shift register
4.Discuss about synchronous counters
• binary counter:4-bit synchronous binary counter, with parallel load
• Up-down counter
• BCD counter
5.Write the procedure for analyzing a clocked sequential circuit with JK flip flop
• Given a logic diagram. From this ,write the state equations
• Establish the state table
• Draw the state diagram
• Write the flip flop input equations and the output equation, if any.
UNIT -V
1.Explain the procedure for analyzing an asynchronous sequential circuit with SR
latches with example
• Given an asynchronous sequential circuit with SR latch
• Label each latch output with Yi and its external feedback path with Yi
• Derive the Boolean functions for the Si & Ri input in each latch
• check whether SR=0 for each NOR latch or whether S'R' =0 for each
NAND latch
• Evaluate Y=S+R'y for each NOR latch or Y=S'+Ry for each NAND latch
• Construct a map with the y's representing the rows and the x inputs
representing the columns
• Plot the value of Y=Y1Y2.......in the map
• Circle all stable states where Y=y. The resulting map is then the transition
table.
2.Explain the procedure for designing an asynchronous sequential circuit with an
example obtain a primitive flowtable from the given design specifications
• Reduce the flow table by merging rows in the primitive flowtable
• Assign binary values to the state variables to obtain the transition tables
Assign output values to unstable states to obtain the output maps
• Simplify the Boolean functions of the excitations and output variables and
draw the logic diagram.
3.Discuss in detail the procedure for reducing the flowtable with an example
• Determine all the compatible pairs by using implication table
• Find the maximal compatibles using the merger diagram
• Find the minimal collection of compatibles that covers all the states and is
closed
• The minimal collection is used to merge the rows of the flow table
4.write short notes on race-free state assignment
• Three row flowtable example
• Four row flowtable example
• shared row method
• Multiple row method
5.Explain in detail Hazards
• Hazards in combinational circuits
_ Explanation with example
_ (Static 1-Hazard,Static 0-Hazard&Dynamic Hazard)
• Hazards in sequential circuit
_ Implementation with SR latches
_ Essential Hazards.
CS2202 / 141302 Digital Principles and Systems Design IMPORTANT 16marks
(DPSD)
Subject Code : CS2202
Subject Name :Digital Principles and Systems Design
Department :CSE and IT
Semester :3
16 Marks
UNIT I
1 (i). Express the Boolean function F =A+B’C in sum of minterms
(ii) Express the Boolean function F=xy+x’z in production of maxterms.
Solution:
F = A+B’C
= A’B’C’+AB’C+AB’C+ABC’+ABC
= m1 + m4 + m5 + m6 + m 7
=_m (1,4,5,6,7)
F = XY+X’Z
= (X+Y+Z)(X+Y’+Z)(X’+Y+Z)(X’+Y+Z’)
= M 0 M 2 M 4 M 5
= P (0,2,4,5)
2.Simplify the Boolean function F(A,B,C,D)= _(0,6,8,13,14) Together with the don’t
care condition d=_(2,4,10)and then express the simplified function in sum of
minterms.
¨ Using 4-variable map simplify the function as
F=B’D’+CD’+ABC’D
¨Represent the simplified function in SOP from as
F=_(0,2,6,8,10,13,14)
3.Implement the Boolean function F(X,Y,Z)=(1,2,3,4,5,7)with NAND gates
¨Simplify the function using 3-varabile map and express it SOP from as
F=XY’+X’Y+Z
¨Draw a NAND gate for each product term of the expression. This gives a
group of first level gates.
¨Draw a single gate using the AND –invert or the invert -OR graphic simple
in the second level, with inputs coming from outputs of first level gates.
4. Simplify the Boolean function F(A,B,C,D) =_(0,2,3,5,7,8,9,10,11,13,15)and find the
prime implicants and essential prime implicants
¨ Simplify the expression using 4-varible map,
¨ Prime implicants are :CD,B’C,AD AND AB’
¨ Essential prime implicants are :CD,B’C,AD AND AB’
¨ Different simplified versions are :BD and B’D’
F=BD+B’D+CD+AD
F=BD+B’D+CD+AB’
F=BD+B’D+B;C+AD
F=BD+B’D’+B;C+AB’
5.Minimize the following function sing Quine Mc Cluskey Method
• List all minterms in the binary form
• Arrange minterms according to categories of 1 in a table
• Compare each binary number with every term in the next higher category and if
they differ only one position put a check mark and copy the term in the next
column with a – in the position that they differed.
• Continue the process until no further elimination of literals
• List the prime implicants
• Select the minimum number of prime implicants
UNIT II
1.Design a full adder with inputs x,y,z and two outputs S and C . The circuit performs
x+y+z, z is the input carry, C is the output carry and S is the Sum.
• Truth table for full adder
• Simplify using K map
• Draw the logic diagram using AND and XOR gate
• Draw the logic diagram using 2 half adders
2. Design a BCD adder.
• Explanation on BCD addition
o Add 2 BCD numbers using ordinary binary addition
o If sum >=9 no correction is needed
o If sum >=9 or if a carry is generated the sum is invalid
o To correct the invalid sum add 0110 to the sum. If a carry results from this
addition add it to the next higher order BCD digits.
• Draw the truth table with 4 inputs
• Simplify output using 4 variable map
• Draw the logic diagram
3. Design a logic circuit that accepts a 4-bit Grey code and converts it into 4-bit
binary code
• Draw the truth table with 4 inputs G3,G2,G1andG0 and 4 0utputs D,C,B and
A.
• Simplify the columns A,B,C and D using 4-variables map
A=(G3 XOR G2)XOR(G1 XOR G0)
B=G3 XOR G2 XOR G1
C=G3 XOR G2
D=G3
• Draw the logic diagram using xor gates with G3,G2,G1 and G0 as Input and
A,B,C and D as output
4.Write short notes on: BCD adder, Binary multiplier and Magnitude Comparator
o BCD adder truth table
o Block diagram of BCD adder
o Logic diagram for 2-bit by 2-bit binary multiplier
o 4-bit magnitude comparator
5.Explain in detail the Hardware Description Languages
• Module representation
• Gate delays
• Boolean expressions
• User -defined primitives
• Explanation of the above with suitable examples
UNIT-III
1.Draw the circuit for 3-to-8-decoder and implement the functions
F1(A,B,C)=II(0,1,3,7)
F2(A,B,C)=II(2,3,7) using 3-to-8-decoder
• Truth table for a 3-to-8-decoder(i/p: E,A,B,C and o/p:Y7-Y0)
• Logic diagram
• Block diagram of 3:8 decoder using IC74LS183 WITH A,B,C as input and
F1,F2 as output
2.Draw the circuits for Decimal to BCD encoder, Octal-to-Binary encoder & Priority
encoder
• Decimal to BCD encoder-logic symbol(74LS147,truth table)
• Octal to binary encoder truth table with inputs D0 - D7 and outputs A , B
and C
• Logic diagram of Octal to binary encoder: A=D4+D5+D6+D7;
B=D2+D3+D6+D7; C=D1+D3+D5+D7
• Priority encoder - truth table with i/ps : D0,D1,D2,D3 and o/ps: Y1,Y0,V
• Logic diagram of Priority encoder where Y1=D2+D3,Y0=D3+D1D2',
V=D1+D2+D3
3.Implement the following boolean function using 8:1 multiplier
• F(A,B,C,D)=A'BD'+ACD+B'CD+A'B'CD+A'BC'D+A'B'C'D
• Draw the Truth table for the above SOP(I/P's:A,B,C,D, o/p: Y)
• Draw the implementation table 8:1 multiplexer, where
D0=0,D2=0,D1=D3=1,D4=D5=D6=A',D7=A
4.Implement full subtractor using demultiplexer
• Truth table of full subtractor(i/p:A,B,Bin,o/pL
,Bout) • D=F(A,B,C)= m(1,2,4,7)
• Bout=F(A,B,C)= m(1,2,3,7)
• Draw 1:8 demultiplexer with the input Din=1 and output D and Bout.
5.Implement the following Boolean function with a PLA
F1(A,B,C)= m(0,1,2,4)
F2(A,B,C)= m(0,5,6,7)
• Simplify F1 and F2 using k-map
F1(A,B,C)=(AB+AC+BC)'
F2(A,B,C)=AB+AC+A'B'C'
• Draw the PLA programming table with minterms
AB,AC,BC&A'B'C'
UNIT IV
1. Draw the state diagram and characteristic equations of T,D and JK flip flop
• Characteristic equation of T flip flop: Q(t+1)=TQ'+T'Q
• Characteristic equation of D flip flop: Q(t+1)=D
• Characteristic equation of JK flip flop: Q(t+1)=JQ'+K'Q
• state diagrams of T,D and JK flip flops
2. Write short notes on state reduction and state assignment in Sequential circuit
design
State reduction
• Given a state diagram of a sequential circuit. Establish the
corresponding state table
• Find the equivalent states that produce the same output for every
input and the same next state
• Draw the reduced state table by removing one of the equivalent
state
• Draw the corresponding reduced state diagram
State assignment
• Binary assignment
• Gray code assignment
• One-hot assignment
3. Discuss in detail shift registers
• Block diagram of 4-bit shift register
• Serial transfer of information
• serial addition using shift register
• Universal shift register
4.Discuss about synchronous counters
• binary counter:4-bit synchronous binary counter, with parallel load
• Up-down counter
• BCD counter
5.Write the procedure for analyzing a clocked sequential circuit with JK flip flop
• Given a logic diagram. From this ,write the state equations
• Establish the state table
• Draw the state diagram
• Write the flip flop input equations and the output equation, if any.
UNIT -V
1.Explain the procedure for analyzing an asynchronous sequential circuit with SR
latches with example
• Given an asynchronous sequential circuit with SR latch
• Label each latch output with Yi and its external feedback path with Yi
• Derive the Boolean functions for the Si & Ri input in each latch
• check whether SR=0 for each NOR latch or whether S'R' =0 for each
NAND latch
• Evaluate Y=S+R'y for each NOR latch or Y=S'+Ry for each NAND latch
• Construct a map with the y's representing the rows and the x inputs
representing the columns
• Plot the value of Y=Y1Y2.......in the map
• Circle all stable states where Y=y. The resulting map is then the transition
table.
2.Explain the procedure for designing an asynchronous sequential circuit with an
example obtain a primitive flowtable from the given design specifications
• Reduce the flow table by merging rows in the primitive flowtable
• Assign binary values to the state variables to obtain the transition tables
Assign output values to unstable states to obtain the output maps
• Simplify the Boolean functions of the excitations and output variables and
draw the logic diagram.
3.Discuss in detail the procedure for reducing the flowtable with an example
• Determine all the compatible pairs by using implication table
• Find the maximal compatibles using the merger diagram
• Find the minimal collection of compatibles that covers all the states and is
closed
• The minimal collection is used to merge the rows of the flow table
4.write short notes on race-free state assignment
• Three row flowtable example
• Four row flowtable example
• shared row method
• Multiple row method
5.Explain in detail Hazards
• Hazards in combinational circuits
_ Explanation with example
_ (Static 1-Hazard,Static 0-Hazard&Dynamic Hazard)
• Hazards in sequential circuit
_ Implementation with SR latches
_ Essential Hazards.
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