080250011- COMPUTER ORGANIZATION AND ARCHITECTURE May/June 2013 Question paper

[SriNee]

Anna University , Coimbatore

B.E/B.TECH. DEGREE EXAMINATION, MAY/JUNE 2013
Fourth Semester
Computer Science and Engineering
080250011- COMPUTER ORGANIZATION AND ARCHITECTURE
(Regulation 2008/2010)

Degree : B.E./B.Tech

Year : II

Sem : 04

Branch : CSE

Subject Code/Name : 080250011- COMPUTER ORGANIZATION AND ARCHITECTURE

Type : May/June 2013 Question Paper

Content Details : 080250011- COMPUTER ORGANIZATION AND ARCHITECTURE May/June 2013 Question paper

---

B.E/B.TECH. DEGREE EXAMINATION, MAY/JUNE 2013

Fourth Semester

Computer Science and Engineering

080250011- COMPUTER ORGANIZATION AND ARCHITECTURE

(Regulation 2008/2010)

PART A-(10*2=20 marks)


1.What is meant by an addressing mode? Mention most important of them.
2.State the rule for floating point addition.
3.Write the register transfer sequence to read a word from memory.
4.What is a micro-program sequencer?
5.What is meant by hazard in pipelining? Define data and control hazards.
6.Why is branch prediction algorithm needed? Differentiate between the static and dynamic techniques.
7.An address is specified by 24 bits and the corresponding memory space by 16 bits
8.What is meant by an interleaved memory?
9.Distinguish between isolated and memory-mapped I/O?
10.Mention the advantages of USB.



PART B-(5*16=80 marks)

11. (a) (i) Explain different types of instructions with examples. Compare their relative merits and
Demerits.
(ii) Explain with an example how to multiply two unsigned binary numbers.
Or
(b) Explain the design of ALU in detail.

12. (a) Explain the design of micro-programmed control unit in detail.
Or
(b) (i) Explain the execution of a three operand instruction using multiple bus organization.
(ii) Write notes on nano programming.

13. (a) (i) Explain a 4-stage instruction pipeline. Also the issues affecting pipeline performance.
(ii) Explain dynamic branch prediction technique.
Or
(b) (i) Explain the relation between pipelined execution and instruction feature.
(ii) Describe the techniques for handling control hazards in pipelining.

14. (a) (i) Draw the block diagrams of two types of DRANs and explain.
(ii) Explain address translation method in virtual memory.
Or
(b) (i) Explain the various mapping techniques associated with cache memories.
(ii) Write short note on magnetic hard disks.

15. (a) Explain the following:
(i) Interrupts
(ii) Buses
Or
(b) (i) Explain interface circuits.
(ii) Discuss about PCI buses.

[V SIVA]

+1